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NXP Semiconductors /MIMXRT1021 /CCM_ANALOG /MISC1_SET

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Interpret as MISC1_SET

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PFD_480_AUTOGATE_EN)PFD_480_AUTOGATE_EN 0 (PFD_528_AUTOGATE_EN)PFD_528_AUTOGATE_EN 0 (IRQ_TEMPPANIC)IRQ_TEMPPANIC 0 (IRQ_TEMPLOW)IRQ_TEMPLOW 0 (IRQ_TEMPHIGH)IRQ_TEMPHIGH 0 (IRQ_ANA_BO)IRQ_ANA_BO 0 (IRQ_DIG_BO)IRQ_DIG_BO

Description

Miscellaneous Register 1

Fields

PFD_480_AUTOGATE_EN

This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off
PFD_528_AUTOGATE_EN

This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off
IRQ_TEMPPANIC

This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature
IRQ_TEMPLOW

This status bit is set to one when the temperature sensor low interrupt asserts for low temperature
IRQ_TEMPHIGH

This status bit is set to one when the temperature sensor high interrupt asserts for high temperature
IRQ_ANA_BO

This status bit is set to one when when any of the analog regulator brownout interrupts assert
IRQ_DIG_BO

This status bit is set to one when when any of the digital regulator brownout interrupts assert

Links

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Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data